Analog VGA Connector Pinouts for HD15 Shells

Pin numbering in female connector

Here's a text I grabbed from the net (with banners and stuff deleted)... I would link to it - but I'm not sure how long this kind of stuff sits around, so here's the original link http://www.epanorama.net/documents/pc/vga_bd15.html.

Pinout

1       Red out *
2       Green out *
3       Blue out *
4       Monitor ID 2 in
5       Ground
6       Red return
7       Green return
8       Blue return
9       no pin
10      Sync return
11      Monitor ID 0 in
12      Monitor ID 1 in
13      Horizonal Sync out
14      Vertical Sync out
15      reserved (monitor ID 3)

Signals marked with * are analogue 0.7V p-p positive signals to 75 ohm load. All other signals are TTL level signals.

Here is an ASCII pinout diagram for those who prefer it:

                                                                 6
 1 Red (Analog)   6 Red   Return    11 (ID0) GND (Color)     11. . . 1
 2 Green (Analog) 7 Green Return    12 (ID1) NC (Color)        . . .
 3 Blue (Analog)  8 Blue  Retuen    13 Horzontal Sync          . . .
 4 Reserved       9 No Connect      14 Vertical  Sync          . . .
 5 Ground        10 Ground          15 No Connect              . . .
                                                             15  10  5

Monitor ID detection pin assignments

4    11   12
ID2  ID0  ID1

n/c  n/c  n/c   no monitor
n/c  n/c  GND   Mono monitor which does not sopport 1024x768
n/c  GND  n/c   Color monitor which does not support 1024x768
GND  GND  n/c   Color monitor which supports 1024x768

GND menas connected to ground
n/c means that the pin has not bee connected anywhere

This monitor type detection is becoming more and more obsolete nowadays, because more and mode intelligence is integrated to the monitor. New plug-and-play monitors communicate with the computer according to VESA DDC standard.

VESA DDC

VESA Display Data Channel is a method for integrating digital interface to VGA conenctor to be able the monitor and grapahics card to communicate. There are two different levels of DDC: DDC1 and DDC2.

DDC1

DDC1 allows the monitor to tell it's parapeters to the computer. The following VGA card connector pins had to be changed to allow DDC1 fuctions:

pin    new function
 9     Optional +5V output from graphics card
12     Data from display
14     Standard vertical sync signal which works also as data clock
15     Monitor ID3

When the graphics card detects data on data-line it starts to read the data coming from the monitor synchronous to the vertical sync pulse. Vertical sync pulse frequency can be increased up to 25 KHz for the time of the data transfer if a DDC1 compliant monitor is found (be sure not to send those high frequencies to non DDC1 monitors!).

DDC2

DDC2 allows bidirectional communication: monitor can tell it's parameters and computer can adjust monitor settings. The bidirectional data bus is a syncronous data bus similar to Access Bus and is based on I2C technology. Tho following pins had to be changed to to enable DDC2 to work:

pin    new function
 9     Optional +5V output from graphics card
12     Bidirectional data line (SDA)
15     Data clock (SLC)

The signals in the data bus are standard I2C signals. The computer provides 15 kohm pullup for the SDA and SLC lines. Monitor must provide 47 kohm pull-up on SCLK line.

NOTE: If the optional +5V power output pin is used, a special DDC/VGA connector must be used to to provide proper sequencing. The +5V output voltage must be withing +/-5% range and tha card must be able to supply at least 300 mA current (maximum 1A).

VESA DPMS power saving

VESA has defined a standard method for computer to tell monitor when to go to power saving mode. This power saving mode is controlled by changing the sync signals according the table below:

                NORMAL          STANDBY         SUSPENDED       OFF
H-sync          On              Off             On              Off
V-sync          On              On              Off             Off
Power level     100%            80%             <30W            <8W

Original Text Courtesy of: Tomi Engdahl <Tomi.Engdahl@iki.fi>

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